This invention relates generally to CMOS register circuits and, more particularly, to a self-correcting SEU-hardened CMOS register.
A standard D-type CMOS register of the type which is well known in the prior art consists of an input master loop and an output slave loop. Input data is locked into the master loop on a first transition (e.g. rising edge) of a clock pulse. On the next clock pulse transition (e.g. falling edge), the data previously stored in the master loop is locked into the slave loop, and the master loop is isloated from the circuit's output. During this time period (e.g. when the clock is held low for an extended period of time), SEU (Single Event Upset) -hardness is of extreme concern.
As is well known, the earth is constantly being bombarded with very high energy particles; the worst case situation occurring upon the impingement of a 150-MeV Krypton ion which produces a worst case charge of four pico coulombs which decays exponentially with a time constant of 250 picoseconds. Such particles can generate very high negative instantaneous currents when striking a CMOS device which may result in the grounding of a junction. It should be apparant that if any one of the nodes in the slave loop of a CMOS register is momentarily grounded by such a particle during the period of time when the clock is low, the state of the loop may be forced into compliance with a logic state of zero at that node. This in turn may result in a register output which is incorrect. This can be extremely disadvantageous if, for example, the registers are programmed to define a particular mode of operation which remains defined for long periods of time, perhaps even months. One known CMOS register circuit which was designed to solve this problem utilizes triple redundancy and voting logic. The circuit incorporates three parallel registers, each of which has a voting circuit in its slave loop feedback. The outputs of all three slave loops are coupled into all three voting circuits such that the loop feedback for each of the three loops is that for which at least two of the loops are in agreement. Thus, if a SEU-induced error occurs in one of the slave loop circuits, its voting logic will override the error and drive the loop back into conformance with the other two loops. It should be apparent, that this approach results in a circuit which is bulky, includes a large number of devices, occupies a relatively large chip area, and presents three times the input load capacitance when compared to a nonredundant register.
In yet another attempt at providing a circuit which is immune to single event upsets caused by incident high energy cosmic particles, hardening resistors have been employed in the propagation path. Unfortunately, this renders the circuitry less useful for high speed applications.